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                         WD65C816 Opcode Reference                   02/20/93
                            by Eric D. Shepherd

Cycle Time Adjustments

      16A: Add 1 if using 16-bit memory and accumulator
      16B: Add 2 if using 16-bit memory and accumulator
      B:   Add 1 if conditional branch is taken
      C:   Add 1 if index crosses bank boundary
      D:   Add 1 if status register's Decimal bit is set
      I:   Add 1 if using 16-bit index registers
      M:   Add 7 for each byte copied
      N:   Add 1 if in native mode
      P:   Add 1 if branch crosses page boundary in emulation mode
      Z:   Add 1 if DP is not on a page boundary

Instruction Hex Cycle Time Status Reg. Notes

ADC #imm 69 2 [16A,D] nv—-zc Add memory to A with

                                                      carry.

ADC abs 6D 4 [16A,D] ADC longabs 6F 5 [16A,D] ADC dp 65 3 [16A,Z,D] ADC (dp) 72 5 [16A,Z,D] ADC [dp] 67 6 [16A,Z,D] ADC abs,X 7D 4 [16A,C,D] ADC abslong,X 7F 5 [16A,D] ADC abs,Y 79 4 [16A,C,D] ADC dp,X 75 4 [16A,Z,D] ADC (dp,X) 61 6 [16A,Z,D] ADC (dp),Y 71 5 [16A,Z,C,D] ADC [dp],Y 77 6 [16A,Z,D] ADC ofs,S 63 4 [16A,D] ADC (ofs,S),Y 73 7 [16A,D]


AND #imm 29 2 [16A] n—–z- And A with memory. AND abs 2D 4 [16A] AND abslong 2F 5 [16A] AND dp 25 3 [16A,Z] AND (dp) 32 5 [16A,Z] AND [dp] 27 6 [16A,Z] AND abs,X 3D 4 [16A,C] AND abslong,X 3F 5 [16A] AND abs,Y 39 4 [16A,C] AND dp,X 35 4 [16A,Z] AND (dp,X) 21 6 [16A,Z] AND (dp),Y 31 5 [16A,Z,C] AND [dp],Y 37 6 [16A,Z] AND ofs,S 23 4 [16A] AND (ofs,S),Y 33 7 [16A]


ASL 0A 2 n—–zc Shift left memory or A. ASL abs 0E 6 [16B] ASL dp 06 5 [16B,Z] ASL abs,X 1E 7 [16B] ASL dp,X 16 6 [16B,Z]


BCC relbyte 90 2 [B,P] ——– Branch if carry clear. BCS relbyte B0 2 [B,P] ——– Branch if carry set. BEQ relbyte F0 2 [B,P] ——– Branch if equal (z=0).


BIT #imm 89 2 [16A] ——z- Test memory with bits

                                                      from A.

BIT abs 2C 4 [16A] nv—-z- BIT dp 24 3 [16A,Z] BIT abs,X 3C 4 [16A,C] BIT dp,X 34 4 [16A,Z]


BMI relbyte 30 2 [B,P] ——– Branch if minus (n=1). BNE relbyte D0 2 [B,P] ——– Branch if not equal. BPL relbyte 10 2 [B,P] ——– Branch if positive. BRA relbyte 80 2 [P] ——– Branch always.


BRK byte 00 7 [N] —-01– Software break BRK 00 —101– (sets b in emulation

                                                      mode).

——————————————————————————- BRL relword 82 4 ——– Branch always long. BVC relbyte 50 2 [B,P] ——– Branch if overflow

                                                      clear.

BVS relbyte 70 2 [B,P] ——– Branch if overflow set.


CLC 18 2 ——-0 Clear carry bit. CLD D8 2 —-0— Clear decimal bit. CLI 58 2 —–0– Clear interrupt disable

                                                      bit.

CLV B8 2 -0—— Clear overflow bit.


CMP #imm C9 2 [16A] n—–zc Compare A with memory. CMP abs CD 4 [16A] CMP abslong CF 5 [16A] CMP dp C5 3 [16A,Z] CMP (dp) D2 5 [16A,Z] CMP [dp] C7 6 [16A,Z] CMP abs,X DD 4 [16A,C] CMP abslong,X DF 5 [16A] CMP abs,Y D9 4 [16A,C] CMP dp,X D5 4 [16A,Z] CMP (dp,X) C1 6 [16A,Z] CMP (dp),Y D1 5 [16A,Z,C] CMP [dp],Y D7 6 [16A,Z] CMP ofs,S C3 4 [16A] CMP (ofs,S),Y D3 7 [16A]


COP byte 02 7 [N] —-01– Coprocessor enable.


CPX #imm E0 2 [I] n—–zc Compare X with memory. CPX abs EC 4 [I] CPX dp E4 3 [I,Z]


CPY #imm C0 2 [I] n—–zc Compare Y with memory. CPY abs CC 4 [I] CPY dp C4 3 [I,Z]


DEC 3A 2 n——c Decrement A or memory. DEC abs CE 6 [16B] DEC dp C6 5 [16B,Z] DEC abs,X DE 7 [16B] DEC dp,X D6 6 [16B,Z]


DEX CA 2 n——c Decrement X register. DEY 88 2 n——c Decrement Y register.


EOR #imm 49 2 [16A] n——c Exclusive-OR A with

                                                      memory.

EOR abs 4D 4 [16A] EOR abslong 4F 5 [16A] EOR dp 45 3 [16A,Z] EOR (dp) 52 6 [16A,Z] EOR [dp] 47 6 [16A,Z] EOR abs,X 5D 4 [16A,C] EOR abslong,X 5F 5 [16A] EOR abs,Y 59 4 [16A,C] EOR dp,X 55 4 [16A,Z] EOR (dp,X) 41 5 [16A,Z] EOR (dp),Y 51 6 [16A,Z,C] EOR [dp],Y 57 4 [16A,Z] EOR ofs,S 43 4 [16A] EOR (ofs,S),Y 53 7 [16A]


INC 1A 2 n——c Increment A or memory. INC abs EE 6 [16B] INC dp E6 5 [16B,Z] INC abs,X FE 7 [16B] INC dp,X F6 6 [16B,Z]


INX E8 2 n——c Increment X register. INY C8 2 n——c Increment Y register.


JMP abs 4C 3 ——– Jump. JMP (abs) 6C 5 JMP (abs,X) 7C 6


JML abslong 5C 4 ——– Jump long. JML [dp] DC 6


JSL abslong 22 8 ——– Jump to subroutine

                                                      long.

——————————————————————————- JSR abs 20 6 ——– Jump to subroutine. JSR (addr,X) FC 8


LDA #imm A9 2 [16A] n—–z- Load accumulator with

                                                      memory.

LDA abs AD 4 [16A] LDA abslong AF 5 [16A] LDA dp A5 3 [16A,Z] LDA (dp) B2 5 [16A,Z] LDA [dp] A7 6 [16A,Z] LDA abs,X BD 4 [16A,C] LDA abslong,X BF 5 [16A] LDA abs,Y B9 4 [16A,C] LDA dp,X B5 4 [16A,Z] LDA (dp,X) A1 6 [16A,Z] LDA (dp),Y B1 5 [16A,Z,C] LDA [dp],Y B7 6 [16A,Z] LDA ofs,S A3 4 [16A] LDA (ofs,S),Y B3 7 [16A]


LDX #imm A2 2 [I] n—–z- Load X register with

                                                      memory.

LDX abs AE 4 [I] LDX dp A6 3 [I,Z] LDX abs,Y BE 4 [I,C] LDX dp,Y B6 4 [I,Z]


LDY #imm A0 2 [I] n—–z- Load Y register with

                                                      memory.

LDY abs AC 4 [I] LDY dp A4 3 [I] LDY abs,X BC 4 [I,C] LDY dp,X B4 4 [I,Z]


LSR 4A 2 n—–zc Logical shift A or

                                                      memory right.

LSR abs 4E 6 [16A] LSR dp 46 5 [16A,Z] LSR abs,X 5E 7 [16A] LSR dp,X 56 6 [16A,Z]


MVN byte,byte 54 [M] ——– Move memory negative

                                                      (srcbank, destbank).

MVP byte,byte 44 [M] ——– Move memory positive

                                                      (srcbank, destbank).
                                                      * X = source address
                                                        Y = target address
                                                        A = length -1

——————————————————————————- NOP EA 2 ——– No operation.


ORA #imm 09 2 [16A] n—–z- Or A with memory. ORA abs 0D 4 [16A] ORA abslong 0F 5 [16A] ORA dp 05 3 [16A,Z] ORA (dp) 12 5 [16A,Z] ORA [dp] 07 6 [16A,Z] ORA abs,X 1D 4 [16A,C] ORA abslong,X 1F 5 [16A] ORA abs,Y 19 4 [16A,C] ORA dp,X 15 4 [16A,Z] ORA (dp,X) 01 6 [16A,Z] ORA (dp),Y 11 5 [16A,Z,C] ORA [dp],Y 17 6 [16A,Z] ORA ofs,S 03 4 [16A] ORA (ofs,S),Y 13 7 [16A]


PEA abs F4 5 ——– Push effective absolute

                                                      address.

PEI (dp) D4 6 [Z] ——– Push effective indirect

                                                      address.

PER relword 62 6 ——– Push effective relative

                                                      address.

PHA 48 3 [16A] ——– Push accumulator. PHB 8B 3 ——– Push data bank

                                                      register.

PHD 0B 4 ——– Push direct page

                                                      register.

PHK 4B 3 ——– Push program bank

                                                      register.

PHP 08 3 ——– Push processor status

                                                      register.

PHX DA 3 [I] ——– Push X register. PHY 5A 3 [I] ——– Push Y register.


PLA 68 4 [16A] n—–z- Pull accumulator. PLB AB 4 n—–z- Pull data bank

                                                      register.

PLD 2B 5 n—–z- Pull direct page

                                                      register.

PLP 28 4 nvmxdizc Pull processor status

                                                      register.

PLX FA 4 [I] n—–z- Pull X register. PLY 7A 4 [I] n—–z- Pull Y register.


REP #imm C2 3 ???????? Reset processor status

                                                      register bits.

——————————————————————————- ROL 2A 2 n—–zc Rotate A or memory

                                                      right.

ROL abs 2E 6 [16A] ROL dp 26 5 [16A,Z] ROL abs,X 3E 7 [16A] ROL dp,X 36 6 [16A,Z]


RTI 40 6 [N] ???????? Return from interrupt. RTI 40 6 ??11???? (emulation mode). RTL 6B 6 ——– Return from subroutine

                                                      long.

RTS 60 6 ——– Return from subroutine.


SBC #imm E9 2 [16A,D] nv—-zc Subtract memory from

                                                      A with borrow.

SBC abs ED 4 [16A,D] SBC abslong EF 5 [16A,D] SBC dp E5 3 [16A,Z,D] SBC (dp) F2 5 [16A,Z,D] SBC [dp] E7 6 [16A,Z,D] SBC abs,X FD 4 [16A,C,D] SBC abslong,X FF 5 [16A,D] SBC abs,Y F9 4 [16A,C,D] SBC dp,X F5 4 [16A,Z,D] SBC (dp,X) E1 6 [16A,Z,D] SBC (dp),Y F1 5 [16A,Z,C,D] SBC [dp],Y F7 6 [16A,Z,D] SBC ofs,S E3 4 [16A,D] SBC (ofs,S),Y F3 7 [16A,D]


SEC 38 2 ——-1 Set carry bit. SED F8 2 —-1— Set decimal bit. SEI 78 2 —–1– Set interrupt disable

                                                      bit.

SEP #imm E2 3 ???????? Set processor status

                                                      register bits.

——————————————————————————- STA abs 8D 4 [16A] ——– Store A to memory. STA abslong 8F 5 [16A] STA dp 85 3 [16A,Z] STA (dp) 92 5 [16A,Z] STA [dp] 87 6 [16A,Z] STA abs,X 9D 5 [16A] STA abslong,X 9F 5 [16A] STA abs,Y 99 5 [16A] STA dp,X 95 4 [16A,Z] STA (dp,X) 81 6 [16A,Z] STA (dp),y 91 6 [16A,Z] STA [dp],y 97 6 [16A,Z] STA ofs,S 83 4 [16A] STA (ofs,S),Y 93 7 [16A]


STP DB 3 ——– Stop the processor.


STX abs 8E 4 [I] ——– Store X register to

                                                      memory.

STX dp 86 3 [I,Z] STX dp,Y 96 4 [I,Z]


STY abs 8C 4 [I] ——– Store Y register to

                                                      memory.

STY dp 84 3 [I,Z] STY dp,X 94 4 [I,Z]


STZ abs 9C 4 [16A] ——– Store zero to memory. STZ dp 64 3 [16A,Z] STZ abs,X 9E 5 [16A] STZ dp,X 74 4 [16A,Z]


TAX AA 2 n—–z- Transfer A to X

                                                      register.

TAY A8 2 n—–z- Transfer A to Y

                                                      register.

TCD 5B 2 n—–z- Transfer 16-bit A to

                                                      direct page register.

TCS 1B 2 ——– Transfer A to stack

                                                      pointer.

TDC 7B 2 n—–z- Transfer direct page

                                                      register to A.

——————————————————————————- TRB addr 1C 6 [16B] ——z- Test and reset bits

                                                      against A.

TRB dp 14 5 [16B,Z]


TSB addr 0C 6 [16B] ——z- Test and set bits

                                                      against A.

TSB dp 04 5 [16B,Z]


TSC 3B 2 n—–z- Transfer stack pointer

                                                      to A.

TSX BA 2 n—–z- Transfer stack pointer

                                                      to X register.

TXA 8A 2 n—–z- Transfer X register to

                                                      A.

TXS 9A 2 ——– Transfer X register to

                                                      stack pointer.

TXY 9B 2 n—–z- Transfer X register to

                                                      Y register.

TYA 98 2 n—–z- Transfer Y register to

                                                      A.

TYX BB 2 n—–z- Transfer Y register to

                                                      X register.

——————————————————————————- WAI CB 3 ——– Wait for interrupt. WDM 42 ? ——– Reserved (currently

                                                      NOP).

——————————————————————————- XBA EB 3 n—–z- Exchange the B and A

                                                      accumulators.

XCE FB 2 –??—- Exchange carry and

                                                      emulation bits.

* Append this file to the end of your Shell:SysHelp file. * If you find an error, email me at: * Internet: uerics@mcl.mcl.ucsb.edu * AOL: Sheppy

/data/webs/external/dokuwiki/data/pages/archive/programming/opcode65816.txt · Last modified: 2002/06/05 00:38 by 127.0.0.1

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